1. Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to sequential sizing in physical synthesis.
2. Related Art
The goal of circuit synthesis is to convert a high-level description of a circuit design into an implementation that meets a set of timing constraints, and at the same time optionally optimizes one or more metrics, such as area, leakage power, etc.
FIG. 1 illustrates a circuit design comprising sequential cells that are coupled to combinational logic regions. Circuit design 100 includes sequential cells 102, 106, and 110 that are coupled to combinational logic regions 104 and 108. During optimization, a circuit design (e.g., circuit design 100) is typically partitioned into combinational logic regions (e.g., combinational logic regions 104 and 108) that only have combinational cells, and each combinational logic region is optimized based on one or more metrics. As shown in FIG. 1, sequential cells (e.g., sequential cells 102, 106, and 108) are typically the startpoints and the endpoints of each combinational logic region. The startpoint is usually also referred to as the launch side of the sequential and the endpoint is usually also referred to as the capture side of the sequential. The launch delay typically includes the delay of the CK→Q timing arc in the sequential cell, whereas the capture delay includes the setup time of the sequential, which is represented as the CK→D-pin timing arc in the sequential cell.
Sequential sizing is a crucial step in any physical synthesis system, because it very closely affects the delay of the circuit on the launch as well as the capture sides. Sequential sizing is a particularly difficult problem in physical synthesis because sizing sequential cells affects delays on both the launch and the capture side. Specifically, up-sizing a sequential cell may improve its launch delay, but could degrade the capture delay. Conversely, down-sizing the sequential cell may degrade its launch delay, but could improve the capture delay. Conventional approaches to logic and physical synthesis rely on iterative approaches to optimizing combinational logic (while keeping the sequential cells fixed to their current sizes) and then separately optimizing sequential cells before again iteratively optimizing the combinational logic.